For digital oscilloscopes to compete with analog oscilloscopes in terms of bandwidth, there is a need for a high speed digitizer. Charge coupled analog shift registers operated in a fast-in/slow-out (FISO) mode offer a solution to the high speed digitizer requirement.
A problem with any data sampled system is that of aliasing. With a digital oscilloscope, aliasing can result in a waveform dissimilar to the input waveform. Various methods have been proposed to prevent the user from being "fooled" by the aliased information. One such method is "min-max" where the minimum and maximum of the input signal are measured during the sample period, and this "min-max" information is displayed. This method has proven to be a powerful tool in digital oscilloscopes. However, min-max requires a suitable method of detecting the minimum and maximum signal during each sample period. It would be convenient if the charged couple device (CCD) used for FISO digitization could also be used to provide a high speed min-max signal.
The basis of a charge coupled device itself is the MOS capacitor. FIGS. 1A and 1B show an isolated MOS capacitor formed by a metal electrode 10 deposited on a thermally oxidized 20 p-type silicon substrate 30.
If a positive voltage is applied to the metal electrode 10, the majority carriers in the silicon 30, holes in the case illustrated, are repelled and a potential well 40 is formed at the silicon surface. Initially this potential well is depleted of free carriers.
The channel stop diffusion 50 (p.sup.+ material) limits the lateral extension of the potential well 40 since it keeps the potential of the silicon dioxide-silicon interface near zero. Minority carriers (electrons) thermally generated in or near this potential well 40, will accumulate at the interface in an inversion layer 60.
It has become customary to think of the potential well as a bucket, and of the minority charge as a liquid that partially fills this bucket. The initial distribution of the interface potential 70, plotted with increasing positive value in the downward direction, is used schematically to depict the size of the empty bucket.
When electron charge is introduced under the electrode 10, the effect is to raise the interface potential 70 towards the silicon dioxide interface 80. The new interface potential 90 is represented schematically as the fluid surface of a partially filled bucket. The area between the two surfaces 80 and 90 gives a pictorial representation of the amount of charge much in the manner of a liquid sitting at the bottom of the bucket. It is important to remember that the real charge resides at the surface 80. This model is only useful in depicting qualitatively the processes in a CCD.
Now if two MOS capacitors are placed close together such that their depletion regions overlap, and their potential wells merge or `couple` together, then any mobile minority charge will accumulate at the location with the highest interface potential. In terms of the fluid charge model we can say that the charge flows to the deepest part of the combined well.
We now have the basis for transferring charge in a controlled manner as shown in FIGS. 2A-2E from one electrode to an adjacent electrode. A charge packet injected under one electrode, P1, held at some potential, will spread along the silicon-silicon dioxide interface when the adjacent electrode P2 is turned on to the same or higher potential. When the potential on the first packet under P1 is reduced, the charge is completely transferred to the new location under P2. The timing diagram of the potentials on electrodes P.sub.x is shown in FIG. 2E for three phase operation.
Multiple devices can be tied together serially in this manner to form a charge coupled device. Several packets of charge can be transferred simultaneously along the device.
Normally charge transfer is required in one direction only (i.e. input to output). In order to achieve unidirectional transfer multiple clock phases are required. Four phase, three phase, and two phase devices have all been used successfully. FIG. 3 shows typical operation of a four phase device.
The CCD itself is thus a means to effectively transfer electrical charge and is conventionally used as a delay line for digital signals. The CCD has also been used as an analog delay line which can accept high speed analog information to be read out at slower, more convenient rates.
As an analog delay line the CCD has also been coupled with a separate high speed peak detector and sample and hold circuit for the detection of the minimum and maximum values of an analog signal. Thus in the prior art the CCD serves only as a delay mechanism, and not as a peak detector itself. When the electrical charge gets to the end of the CCD it can be slowly clocked out to an analog-to-digital converter (A/D) and the quantized. Unfortunately, such a system (high speed peak detector, plus sample and hold, followed by CCD delay line, followed by low speed A/D) requires a considerable amount of hardware and cost.